As CMOS technology is scaled down, transistor density of a chip is increased dramatically, which results in the increasing of the complexity of interconnections. In this paper, a novel design of ternary logic based on carbon nanotube FETs (CNFETs) is proposed and compared with the previous CNFET-based ternary logic designs. Especially, in the proposed CNFET-based ternary logic design, different back biasing voltages and diameters of CNFETs are effectively used to achieve ultra-low power consumption. Extensive simulation results using HSPICE are reported to show that the proposed CNFET-based ternary logic gate reduces leakage current and power delay product (PDP) multiple orders of magnitude compared to the previous CNFET-based ternary logic designs.
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